Q: I am currently verifying the PCI Interface in our custom ASIC for 2.0 Compliance. Target Scenario 2.6 requires that the IUT receive configuration cycles which burst two data phases. Currently our design does not support this. STOP# does not get asserted which causes the bus to hang.

Is this a real problem? Will the bridge ever initiate configuration cycles with multiple data phases?

A: Our PCI bridge (Bandit) for the new PCI PowerMac CPUs will only issue Configuration read and write cycles with ONE data phase.

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